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?2004 fairchild semiconductor corporation www.fairchildsemi.com rev.1.0.2 features ? current mode control for main power ? voltage mode control for auxiliary power ? synchronized switching of main and auxiliary power (70khz) ? internal start-up circuit ? internal soft start for auxiliary power ? user defined soft start for main power ? pulse by pulse current limiting ? over load protection (main : latch mode, aux : auto restart mode) ? internal over temperature protection ? vcc under voltage lockout ? line under voltage/ over voltage lockout ? burst mode operation for auxiliary power to reduce the power consumption in the standby mode ? internal high voltage sensefet for auxiliary power application ? smps for pc power ? lcd tv power supply description FSD1000 is a fairchild power switch (fps) that is specially designed for smps of personal computer. this device is a high voltage power sensefet combined with two pwm controllers in a single monolithic device; one is for main power and the other is for auxiliary power. the pwm controllers feature integrated oscillator, under voltage lockout, optimized gate driver and temperature compensated precise current sources for the loop compensation. this device also includes various fault protection circuits such as line under/ over voltage lock out, over voltage protection, over load protection and over temperature protection. compared with discrete mosfet and pwm controller solution, FSD1000 can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity and system reliability typical circuit FSD1000 combo fairchild power switch (fps tm ) figure 1. typical application circuit vcc main output main pwm v fb.main ac in aux pwm v fb.aux aux output main off ls1 ls2 v str output i sense drain gnd i lim s/s
FSD1000 2 internal block diagram figure 2. functional block diagram of FSD1000 5 6 1 11 vref internal bias s q q r osc i delay i fb s q q r r vcc v fb,aux isense gate drive 12 vstr i ch vcc good soft start (10ms) 4output 9.5/13.5v 21v vcc ovp 8 i delay i fb 2v fb.main vcc vcc power off reset (vcc <6v) otp line ovp vcc ovp 9 s q q r gate drive burst r q q s auto restart latch counter /4 burst aux olp 7 line ovp aux off 3 osc 7v s/s ls2 drain gnd i lim ls1 0.8 v 1.0 v 1.4 v 1.68 v main off 4.4 v 2.4 v 2.0 v pwm comparator 0.5 v 0.7 v 4.5v r 3r vcc vref vref main olp vcc good 1:110 0.3v vcc good vcc good time delay (30ms) main olp vth h : d main < 0.67 l : d main < 0.50 i ss
FSD1000 3 pin definitions pin number pin name pin function description 1v fb,aux this pin is for the feedback control of the auxiliary power. this pin is internally connected to the inverting input of the pwm comparator. the collector of an opto-coupler is typically tied to this pin. for stable operation, a capacitor should be placed between this pin and gnd. voltage mode control is employed for the auxiliary power and the duty cycle ratio of internal mosfet for the auxiliary power is proportional to the voltage of this pin. if the voltage of this pin exceeds 4.5v, the over load protection is triggered terminating the switching operation of the main and auxiliary power (auto-restart mode protection). 2v fb,main this pin is for the feedback control of the main power. this pin is internally connected to the inverting input of the pwm comparator. the collector of an opto-coupler is typically tied to this pin. for stable operation, a capacitor should be placed between this pin and gnd. current mode control is employed for the main power and the peak drain current of the external mosfet for the main power is proportional to the voltage of this pin. if the voltage of this pin exceeds 7v, the over load protection is triggered disabling the gating output for the main power (latch mode protection). 3s/s this pin is for the soft start of the main power. soft start time is programmed by a capacitor on this pin. 4 output this pin is for the gate drive of the external mosfet of the main power. 5vcc this pin is the positive supply voltage input. during startup, the power is supplied by an internal high voltage current source that is connected to the vstr pin. when vcc reaches 13.5v, the internal high voltage current source is disabled and the power is supplied from auxiliary transformer winding. 6i sense this pin is for the current sense of the external mosfet for the main power. it is internally connected to the pwm comparator for the main. 7ls1 this pin is for line under voltage detection. when the voltage of this in drops below 1.4v the main power is shutdown. when the voltage drops below 0.8v, the auxiliary power is shutdown. 8ls2 this pin is for line over voltage detection and maximum duty cycle ratio change. the maximum duty cycle ratio is set to be 50% when the voltage of ls2 pin is higher than 2.4v. the maximum duty cycle ratio is increased to 67% when ls2 voltage goes below 2.0v. when the voltage of ls2 goes above 4.4v, the switching operations for the main and auxiliary powers are disabled to protect the switching devices. 9i lim this pin is for the current limit of the auxiliary power. the pulse-by-pulse current limit level of the internal sensefet is programmed by a resistor on this pin. 10 nc 11 drain this pin is the high voltage power sensefet drain. it is designed to drive the auxiliary transformer directly. 12 v str this pin is connected directly to the high voltage dc link. at startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the vcc pin. once vcc reaches 13v, the internal current source is disabled.
FSD1000 4 pin configuration figure 3. pin configuration (top view) 12 11 10 7 8 9 gnd 2 3 6 5 4 gnd FSD1000 gnd 1 gnd 12diph vfb,aux isense vcc out put s/s vfb,main ls1 ls2 ilim nc dr ai n vstr
FSD1000 5 absolute maximum ratings (ta=25 c, unless otherwise specified) parameter symbol value unit maximum vstr pin voltage v str,max 700 v continuous sensefet drain current (t c =25 c) i d 2a dc maximum supply voltage v cc,max 20 v input voltage range v fb,main / v fb,aux -0.3 to v sd v operating ambient temperature t a -25 to +85 c storage temperature range t stg -55 to +150 c
FSD1000 6 electrical characteristics (ta=25 c unless otherwise specified) note: 1. these parameters, although guaranteed, are not 100% tested in production parameter symbol condition min. typ. max. unit sensefet section drain-source breakdown voltage bv dss v cc = 0v, i d = 100 a 700 - - v off-state current i dss v ds = 560v - - 100 a on-state resistance r ds(on) tj = 25 c i d = 100ma - 7.8 9.0 ? tj = 100 c i d = 100ma - 12.9 15.0 ? rising time 2 (1) t r2 v ds = 350v, i d = 500ma - 100 - ns falling time 2 (1) t f2 v ds = 350v, l d = 500ma - 50 - ns leading edge blanking (1) t leb - - 250 - ns pulse-by-pulse current limit i lim with 33 ? resistor between i lim pin and ground pin 0.8 1.0 1.2 a control section switching frequency fosc tj = 25 c 616773khz main feedback source current i fb,main ta = 25 c, v fb,main = 0v 0.6 0.7 0.8 ma shutdown main delay current i delay,main ta = 25 c 5v < v fb,main < v sd,main 3.5 5.0 6.5 ua aux. feedback source current i fb,main ta = 25 c, v fb,aux = 0v 0.3 0.4 0.5 ma shutdown aux. delay current i delay,main ta = 25 c 3v < v fb,aux < v sd,aux 3.5 5.0 6.5 ua maximum duty cycle dmax v fb,aux = 3.5v 1.4v < ls2 < 2v 62 67 72 % maximum duty cycle dmax v fb,aux = 3.5v 2v < ls2 < 4.4v 45 50 55 % minimum duty cycle dmin v fb,aux = 0v - 0 0 % uvlo threshold voltage vstart - 12.5 13.5 14.5 v vstop after turn on 8.5 9.5 10.5 v soft start section soft start current i soft - 354555 ua internal soft start time t ss --10-ms internal time delay t d --30-ms protection section thermal shutdown temperature (tj) (1) t sd (note 1) 140 160 - c shutdown main feedback voltage v sd,main - 6.0 7.0 8.0 v shutdown aux. feedback voltage v sd,aux vfb = 4v 4.0 4.5 5.0 v output section rising time 1 (1) t r1 ta = 25 c, c l = 100pf - 45 150 ns falling time 1 (1) t f1 ta = 25 c, c l = 100pf - 35 150 ns
FSD1000 7 electrical characteristics (continued) (ta=25 c unless otherwise specified) parameter symbol condition min. typ. max. unit line sense section line over voltage bus ovp - 4.0 4.4 5.0 v pwm max duty control voltage max duty - 2.0 2.4 2.8 v hysteresis - - 400 - mv main off voltage main off - 1.17 1.4 1.63 v hysteresis - - 280 - mv aux. off voltage aux off - 0.67 0.8 0.93 v hysteresis - - 200 - mv burst mode section burst mode voltage burst - - 0.7 - v hysteresis - - 200 - mv total device section start up chragng current i ch v cc = 0v, v str = min. 30v - 1.5 2.3 ma operating supply current i op ta = 25 c, v cc = 18v - 4 5 ma
FSD1000 8 typical performance characteristics (some characteristic graphs are normalized at ta= 25 c) -40 -20 0 20 40 60 80 100 120 140 0.7 0.8 0.9 1.0 1.1 1.2 1.3 iop -40 -20 0 20 40 60 80 100 120 140 0.7 0.8 0.9 1.0 1.1 1.2 1.3 ifb_aux -40 -20 0 20 40 60 80 100 120 140 0.7 0.8 0.9 1.0 1.1 1.2 1.3 ifb -40 -20 0 20 40 60 80 100 120 140 0.7 0.8 0.9 1.0 1.1 1.2 1.3 fosc figure 1. normalized operating current vs. temp figure 2. normalized aux feedback current vs. temp figure 3. normalized main feedback current vs. temp figure 4. normalized operating freqency vs. temp figure 5. output source current (ma) vs. temp figure 6. output sink current (ma) vs. temp -40 -20 0 20 40 60 80 100 120 140 200 250 300 350 400 450 500 550 isouce -40 -20 0 20 40 60 80 100 120 140 300 350 400 450 500 550 600 650 700 isink
FSD1000 9 functional description 1. 1. 1. 1. startup : at startup, an internal high voltage current source supplies the internal bias and charges the external capacitor that is connected to the vcc pin as illustrated in figure 4. when vcc reaches 13.5 v, the fps begins switching operation and the internal high voltage current source is disabled. then, the fps continues its normal switching operation unless vcc goes below the stop voltage of 9.5 v and the power is supplied from the auxiliary transformer winding. once the auxiliary power starts up, the main power starts up with a time delay of 30ms. figure 4. internal startup circuit 2. feedback control : FSD1000 has two pwm controllers in a single package; one is for the main power and the other is for the auxiliary power. the pwm block for the main controls the external mosfet, while the pwm block for the auxiliary power controls the internal sensefet. 2.1 feedback control for the main power : figure 5 illustrates the simplified pwm block for the main power. the current mode control is employed for the main power. the voltage of the feedback pin is compared with the current sense voltage for pulse width modulation (pwm). as shown in figure 5, the feedback voltage determines the peak value of the drain current of the external power mosfet for main power. usually opto-coupler is used to implement feedback network. the collector of the opto-coupler transistor is connected to feedback pin and the emitter is connected to the ground pin. for stable operation, a capacitor should be placed between this pin and gnd. 2.2 feedback control for the auxiliary power : figure 6 shows the internal high voltage sensefet together with pwm block for auxiliary power. auxiliary power employs voltage mode control and the feedback pin voltage is compared with internal ramp signal for pulse width modulation (pwm). the pulse-by-pulse current limit level of the sensefet is programmed by an external resistor on the i lim pin. since the sense ratio is 1/110 and the reference voltage of the comparator is 0.3v, the pulse-by-pulse current limit level (i cl ) is given by figure 5. pwm control block for the main power figure 6. pwm control block for the auxiliary power 3. protection circuit : besides pulse-by-pulse current limit, FSD1000 has various self protection functions; over load protections (olp) for main and auxiliary powers, over voltage protection (ovp), line over/under voltage lockout and over temperature protection (otp). because these protection circuits are fully integrated into the ic without external components, the reliability can be improved. in the event of fault conditions such as olp of auxiliary power and 9.5v/13.5v 3 vref internal bias vcc 6 vstr i start vcc good dc link voltage i cl 110 0.3 r lim ------------------------ = a () 6 s q q r isense gate drive 4output i delay i fb 2 v fb.main vcc vcc pwm comparator r 3r osc 5 max duty control 2.0 v 2.4 v ls2 c fb d1 d2 4 11 osc i delay i fb r v fb,aux soft start 9 s q q r gate drive burst osc drain gnd i lim vref vref 1/110 0.3v c fb d1 d2 r lim
FSD1000 10 line under voltage lockout, FSD1000 enters into auto restart operation. once the fault condition occurs, switching is terminated and the sensefet remains off. this causes vcc to fall. when vcc reaches the stop voltage (9.5v), the internal startup circuit charges vcc capacitor up to start voltage (13.5v). when vcc reaches 13.5v, the internal startup circuit is disabled and vcc is discharged down to 9.5v. in this manner, FSD1000 repeats charging and discharging vcc capacitor 4 times. after then, the protection is reset and the FSD1000 resumes its normal operation. in this manner, the auto-restart can alternately enable and disable the switching of the power sensefet until the fault condition is eliminated as shown figure 7. meanwhile, FSD1000 enters into latch mode in the case of vcc ovp, line ovp and main olp and otp. the fault latch is reset only when vcc is fully discharged below 6v by un-plugging the ac line as shown in figure 8. figure 7. auto restart mode protection figure 8. latch mode protection 3.1 over load protection : over load means that the load current exceeds a pre-set level due to an abnormal situation. in this situation, protection circuit should be triggered in order to protect the smps. because of the pulse-by-pulse current limit capability, the maximum peak current through the smps is limited, and therefore the maximum input power is restricted with a given input voltage. if the output consumes beyond this maximum power, the output voltage (vo) decreases below the set voltage. this reduces opto- coupler transistor current increasing feedback voltage (vfb). if the inverting input of pwm comparator reaches its maximum value, d1 is blocked and the current source i delay starts to charge c fb slowly compared to when the current source i fb charges c fb . in this condition, the feedback voltage continues increasing until it reaches olp threshold, and the switching operation is terminated at that time. the olp for the auxiliary power is auto restart mode while olp for the main is latch mode. 3.2 line under voltage lockout : the switching operation for the main power is terminated when the voltage of ls1 drops below 1.4v and the switching operation for auxiliary power is terminated when this voltage goes below 0.8v. 3.3 over voltage protection : in an abnormal situation such as feedback loop open, the supply voltage for FSD1000 (vcc) may rise above the breakdown voltage of the fps. in order to protects the fps from the over voltage damage, FSD1000 employs over voltage protection for vcc. if vcc exceeds 21v, ovp circuit is triggered resulting in a termination of switching operation of both main and auxiliary powers. in order to avoid undesired triggering of ovp during normal operation, vcc should be properly designed to be below 21v. 3.4 line over voltage protection : when the voltage of ls2 rises above below 4.4v, the switching operations for the main and auxiliary powers are disabled to protect the switching devices. 3.5 over temperature protection : the thermal shutdown circuitry senses the junction temperature. the threshold is set at 160 c. when the junction temperature rises above this threshold, the switching operations of main and auxiliary powers are disabled. 4. burst mode operation : in order to minimize the power dissipation in the standby mode, fds1000 has burst operation for the auxiliary power. the fps enters into the burst mode when the feedback voltage decreases as the load decreases. the operation principle of the burst mode is illustrated in figure 9. when the feedback voltage drops below 0.5v, the fps stops the switching operation. then, the output voltage decreases below the set voltage, which increases the feedback voltage. when the feedback voltage rises above 0.7v, the fps resumes the switching operation and the feedback voltage decreases. when the feedback voltage drops below 0.5v again, the fps ceases the vcc 13.5v 9.5v over load of aux restart aux v ds over load removed vcc 13.5v 9.5v otp, vcc ovp, li ne ovp, main olp aux v ds ac power off 6v latch reset ac power on
FSD1000 11 switching operation. in this manner, the burst operation alternately enables and disables the switching of the power mosfet to reduce the switching loss in the standby mode. figure 9. waveforms of burst operation 5. sequence of start-up and shutdown : FSD1000 has a sequence of the startup and shutdown operation between main and auxiliary powers. as can be seen in figure 11, main power starts up with 30 ms time delay after auxiliary power starts up. when the ac line is powered off, the main power shuts down first as the voltage of ls1 pin drops below 1.4v. the auxiliary power shuts down when the voltage of ls1 drops below 0.8v. figure 12 shows the shutdown and restart sequence in the case of auto restart mode protection. when the protection is triggered, main and auxiliary powers shut down together. when FSD1000 restarts, the auxiliary power starts up first and the main power starts up after 30ms. figure 13 shows the shutdown and restart sequence in the case of latch mode protection. when the protection is triggered, main and auxiliary powers shut down together and vcc continues being charged and discharged until vcc is fully discharged. the protection is reset when vcc is discharged below 6v by unplugging the ac line. figure 14 shows the remote on/off of the main power. the remote on/off of the main power is easily implemented using a transistor connected to the cathode of ka431 in the main power feedback network as shown in figure 10. when the transistor is turned on, the current through the opto-coupler increases pulling down the feedback voltage to almost zero. the main starts up with soft-start when the transistor is turned off. figure 10. remote on/off of main power v fb vds 0.50v 0.70v ids vo vo set time main output aux output main off
FSD1000 12 figure 11. typical waveforms (1) figure 12. typical waveforms (2) ac line voltage dc link voltage vcc aux drain current main drain current t ss =10ms t d =30ms ac power on ac power off ac power on 13.5v 9.5v t d =30ms t ss =10ms ls1<1.4v ls1<0.8v vcc aux drain current main drain current t ss =10ms t d =30ms 13.5v 9.5v t d =30ms t ss =10ms olp of aux auto restart
FSD1000 13 figure 13. typical waveforms (3) figure 14. typical waveforms (4) vcc aux drain current main drain current t ss =10ms t d =30ms 13.5v 9.5v t ss =10ms vcc ovp, line ovp, main olp or otp ac power off 6v latch reset ac power on t d =30ms vcc aux drain current main drain current t ss =10ms t d =30ms 13.5v main off by pulling down v fb main on main v fb
FSD1000 14 typical application circuit features ? low standby mode power consumption (<1w at 240vac input and 0.5w load) ? low component count ? enhanced system reliability through various protection functions ? internal soft-start (10ms) 1. schematic application output power input voltage output voltage (max current) pc power supply 110w universal input with voltage doubler main power : 5v (12a), 3.3v (12a) aux. power : 5v (2a) p2 817a 1 2 4 3 gnd_s r210 4. 7k 1 2 ic2 tl431 3 2 1 c203 472 1 2 c201 472 1 2 0 is d201 1 2 3 c108 222,1kv 1 2 r214 10k 1 2 r101 500k 1 2 r206 1k 1 2 r216 10k 1 2 r205 1k 1 2 t1 ei 3329 6 4 14 1 13 5 3 2 8 7 9 10 11 12 3.3v r211 33k 1 2 r201 10 1 2 c114 222,1kv 1 2 c206 2200uf, 10v 2 1 mbrf3060pt gate t rt1 10d9 1 2 gnd_p r212 1k 1 2 c202 472 1 2 r208 3. 2k 1 2 -+ bd1 gsi b660 1 2 3 4 gnd_s is r209 5k 1 2 c208 470uf, 16v 2 1 r111 10k 1 2 d101 uf4007 1 2 c11 0 47uf, 50v 1 2 r108 50k/3w 1 2 r110 30 1 2 d103 1n4745 l201 eer2834 6 4 1 5 3 2 8 9 10 11 12 7 gnd_p l202 2uh 1 2 c105 222/ 3kv 1 2 s1 sw spdt 2 1 3 r213 1k 1 2 c113 1uf 1 2 5v_aux gnd_s q2 2n2222 1 2 3 ic1 tl431 3 2 1 vdc c107 470uf,200v 1 2 d203 gp30g 1 2 d102 uf4004 1 2 gnd_s r203 10 1 2 c205 2200uf, 10v 2 1 c104 222/ 3kv 1 2 c101 473/ 275vac 1 2 c210 100nf 1 2 r112 33 1 2 c207 470uf,16v 2 1 gnd_p r207 33k 1 2 r104 33k/3w 1 2 f1 fuse r107 10/ 0. 5w 1 2 c115 473 1 2 vfb1 c106 470uf,200v 1 2 gate c102 473/ 275vac 1 2 mbrf3060pt vd c r109 30k 1 2 r202 10 1 2 r204 10 1 2 d104 uf4003 1 2 t2 ee1625 6 4 10 1 9 5 3 2 8 7 r103 10k 1 2 c111 103 1 2 gnd_p vfb1 d106 uf4007 1 2 c103 222/ 3kv 1 2 lf1 1 2 gnd_s c109 102 1 2 c112 473 1 2 gnd_p r106 0. 1/ 2w 1 2 jp2 header 3 1 2 3 drain u1 FSD1000 1 2 3 4 5 6 7 8 9 10 14 13 12 11 vfb.aux vfb. mai n s/s out put vcc isense ls1 ls2 i _li m nc gnd gnd vst art drain r102 500k 1 2 gnd_s c209 47nf 1 2 d202 1 2 3 line f ilt er 1 2 vfb2 gnd_p drain 5v vd c c204 472 1 2 gnd_p gnd_s gnd_p ls 0 r105 1k 1 2 d105 1n4745 gnd_p gnd_s ls p1 817a 1 2 4 3 r215 10k 1 2 vfb2 gnd_p d s g q1 fqa10n80 1 3 2
FSD1000 15 2.1 main transformer schematic diagram core : ei3329 bobbin : ei3329 2.2 main transformer winding specification 2.3 main transformer electrical characteristics no pin (s f) wire turns winding method n p/2 1 30.5 1 24 solenoid winding insulation: polyester tape t = 0.050mm, 2layers n 3.3v 10 80.4 6 2 center winding insulation: polyester tape t = 0.050mm, 2layers n 5v 14 12 0.4 6 3 center winding insulation: polyester tape t = 0.050mm, 2layers n p/2 3 50.5 1 24 solenoid winding outer insulation: polyester tape t = 0.050mm, 2layers pin specification remarks inductance 1 - 5 9mh 10% 100khz, 1v leakage inductance 1 - 5 10uh max 2 nd all short *the' ' marks a re start point. 1 2 3 4 5 11 9 8 7 610 +5v +3 .3v n p/2 n p/2 n p/2 n p/2 3 L bobbin bottom top n 3.3v n 5v 12 13 14 3 L
FSD1000 16 3.1 main inductor schematic diagram core : eer2834 bobbin : eer2834 3.2 main inductor winding specification 3.3 main inductor electrical characteristics no pin (s f) wire turns winding method n 5v 1 12 0.4 8 9 center winding insulation: polyester tape t = 0.050mm, 2layers n 3.3v 6 70.4 8 6 solenoid winding insulation: polyester tape t = 0.050mm, 2layers pin specification remarks inductance 1 - 12 15 uh 10% 100khz, 1v *the' ' marks a re start point. 1 2 3 4 5 11 9 8 7 6 10 n 3.3v n 5v n 3.3v 3 L bobbin top n 5v 12 3 L
FSD1000 17 4.1 auxiliary transformer schematic diagram core : ee1625 bobbin : ee1625 4.2 auxiliary transformer winding specification 4.3 auxiliary transformer electrical characteristics no pin (s f) wire turns winding method n p/2 4 50.15 75 solenoid winding n 5v 8 70.5 9 solenoid winding n vcc 2 10.2 25 solenoid winding n p/2 5 60.15 75 solenoid winding pin specification remarks inductance 4 - 6 1.35mh 10% 100khz, 1v leakage inductance 4 - 6 60uh max 2 nd all short *the' ' marks a re start point. 1 2 3 4 5 9 8 7 6 10 +5v n p/2 n p/2 n p/2 n p/2 3 L bobbin bottom top n 5v n vcc 3 L n vcc
FSD1000 18 5. layout auxiliary transformer electrical characteristics
FSD1000 19 package dimensions 12diph-300
FSD1000 7/9/04 0.0m 001 ? 2004 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. ordering information product number package package marking rdson max FSD1000 12-diph FSD1000 9 ?

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